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| www..com MC805256K36 MOSYS 9-Mbit: 256Kx36 Symmetric Pipelined Burst SRAM A6 A7 CE1# CE2 BW4# BW3# BW2# BW1# CE2# VDD VSS CLK WE# CKE# OE# ADV/LD# NC (A18) A17 A8 A9 DQP3 DQ17 DQ18 VDDQ VSSQ DQ19 DQ20 DQ21 DQ22 VSSQ VDDQ DQ23 DQ24 VDD VDD VDD VSS DQ25 DQ26 VDDQ VSSQ DQ27 DQ28 DQ29 DQ30 VSSQ VDDQ DQ31 DQ32 DQP4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (R) Overview The MoSys MC805256K36 is a high performance, low power symmetric pipelined-burst-SRAM (SPSRAM). Fabricated using an advanced low power, high performance CMOS process, the MoSys MC805256K36 is backward pin and function compatible with industry standard 64Kx36 and 128Kx36. With proper implementation, PC boards can work transparently with 64Kx36, 128Kx36 or 256Kx36 configurations, allowing the designer maximum configuration flexibility within a single footprint layout. The MoSys MC805256K36 supports SPSRAM operating modes at maximum burst frequency including indefinite pipelined read or write (3-1-1-1-11-1...) The MC805256K36 is packaged in a standard 100 lead LQFP. Low Power The MC805256K36 affords systems power savings due to the benefits of its proprietary MoSys technology. Making it ideal for convection cooled applications, as well as applications requiring a large amount of SRAM. Part Number Designation Example: MC805256K36L-7R5I Device Designation: MC8:, Series: 05 Organization: 256K36 Package Type: L=LQFP Speed: - 7R5 133MHz -6 166MHz -5 200MHz Temp: I = Industrial Temperature Parameter Cycle Time Symbol tKC tKQ tKQHZ -7R5 7.5 4.2 3.8 -6 6 3.5 3.1 -5 5 3.0 2.9 Units ns ns ns www..com Access Time Clock to High-Z DS15, Rev 0.5 - 10/14/00 Preliminary Information LBO# A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 133-200MHz Speed grades 3-1-1-1 Burst Read 3-1-1-1 Burst Write 3-1-1-1-1-1-1-1... pipelined operation * Symmetric Pipeline No bus turnaround latency allowing 100% bus efficiency * Low Power Low active power Low power ZZ standby mode 2.5V Core power supply (VDD) 2.5-3.3V I/O power supply (V DDQ) * Compatibility Individual Byte Write masking Interleaved and burst address support Three chip enable inputs Clock Enable and Suspend Industry standard 100-Pin pinout * Applications Ideal for high speed, low power data and telecommunications applications ______________________________________________ * High Performance 100 Pin LQFP 20 mm x 14 mm body 0.65 mm nominal pin pitch 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQP2 DQ16 DQ15 VDDQ VSSQ DQ14 DQ13 DQ12 DQ11 VSSQ VDDQ DQ10 DQ9 VSS VDD VDD ZZ DQ8 DQ7 VDDQ VSSQ DQ6 DQ5 DQ4 DQ3 VSSQ VDDQ DQ2 DQ1 DQP1 Page 1 (c) 2000 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 w w w . D a t a S h e e t 4 U . c o m MC805256K36 MOSYS 9-Mbit: 256Kx36 Symmetric Pipelined Burst SRAM (R) MODE A[17:0] CE1#, CE2, CE2# WE# CKE# ADV/LD# BW[4:1]# D Q Address 256Kx36 Bit Memory Array Input Register D Q Control D Q D Q Control Logic CLK Mux Output Register OE# DQ[32:1] DQP[4:1] Functional Block Diagram DS BURST DESELECT READ DS DS WRITE READ WRITE READ WRITE BEGIN READ BEGIN WRITE Command DS READ WRITE BURST Action DESELECT Begin READ Begin WRITE Begin READ Begin WRITE Continue DESELECT READ BURST BURST WRITE BURST WRITE READ BURST BURST READ BURST WRITE www..com State Diagram DS DS DS15, Rev 0.5 - 10/14/00 Preliminary Information Page 2 (c) 2000 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 www..com MC805256K36 MOSYS 9-Mbit: 256Kx36 Symmetric Pipelined Burst SRAM (R) Command Truth Table CE1# CE2 CE2# H X X X L X L X L X L X X X X L X X H X H X H X H X X X X X H X L X L X L X L X X X ZZ L L L L L L L L L L L L L H ADV/ LD# L L L H L H L H L H L H X X WE# X X X X H X H X L X L X X X BWx# X X X X X X X X L L H H X X OE# X X X X L L H H X X X X X X CKE# L L L L L L L L L L L L H X CLK E E E E E E E E E E E E E X Address Used None None None None External Next External Next External Next None Next Current None Operation Deselect Deselect Deselect Continue Deselect Read Start Read Burst Dummy Read Dummy Read Write Start Write Burst Write Abort Write Abort Ignore Clock Sleep Partial Read/Write Truth Table WE# BW4# BW3# BW2# H X X X L L H H L H L H L H H L L H H H L L L L L H H H Address Burst Sequence Tables A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 A[1:0] 00 01 10 11 A[1:0] 01 00 11 10 A[1:0] 10 11 00 01 A[1:0] 11 10 01 00 BW1# X H H H L L H Operation READ WRITE DQ[32:25] & DQP[4] WRITE DQ[24:17] & DQP[3] WRITE DQ[16:9] & DQP[2] WRITE DQ[8:1] & DQP[1] WRITE All DQ & DQP WRITE Abort/NOP Linear Address, LBO#=L st 1 Address nd 2 Address rd 3 Address th 4 Address Interleaved Address, LBO#=H st 1 Address nd 2 Address rd 3 Address th 4 Address www..com DS15, Rev 0.5 - 10/14/00 Preliminary Information Page 3 (c) 2000 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 www..com MC805256K36 MOSYS 9-Mbit: 256Kx36 Symmetric Pipelined Burst SRAM (R) Pin Description Pin Number 83, 50, 49, 48, 47, 46, 45, 44, 81, 82, 99, 100, 32, 33, 34, 35, 36 ,37 96,95, 94, 93 88 87 89 98 97 92 86 85 64 31 29, 28, 25, 24, 23, 22, 19, 18, 13, 12, 9, 8, 7, 6, 3, 2, 79, 78, 75, 74, 73, 72, 69, 68, 63, 62, 59, 58, 57, 56, 53, 52 30, 1, 80, 51 38, 39, 42, 43, 84 14, 15, 16, 41, 65, 66, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 Absolute Maximum Ratings Symbol Parameter VDD VDDQ Vih Vil Ts Core Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Storage Temperature Symbol A[17:0] BW[4:1]# WE# CKE# CLK CE1# CE2 CE2# OE# ADV/LD# ZZ LBO# DQ[32:1] Type Input Input Input Input Input Input Input Input Input Input Input Input I/O Description Processor Addresses Processor host bus byte enables Read/Write Control Clock Enable Processor host bus clock Chip enable Chip enable for depth expansion Chip enable for depth expansion Asynchronous output enable Address Advance/Load# control Low power sleep mode Linear Burst Order Data I/O pins DQP[4:1] NC VDD VSS VDDQ VSSQ 2.5 Volts Ground 2.5 Volts Ground Data Parity I/O pins unused Power Ground I/O Buffer Supply I/O Buffer Ground Min Max 3.6 VDDQ VDD +1.0, VDDQ 3.6 VDDQ +1 Units V V V V C VSSQ-0.5 -65 150 Notes: Max Vih is not to exceed maximum VDDQ Capacitance Symbol CI CIO Parameter Input Capacitance I/O Capacitance Typ 3 4 Max 4 5 Units V V LQFP Thermal Resistance Symbol Parameter JA JC Junction to Ambient Junction to Case Typ 45 9 Units C/W C/W www..com DS15, Rev 0.5 - 10/14/00 Preliminary Information Page 4 (c) 2000 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 www..com MC805256K36 MOSYS 9-Mbit: 256Kx36 Symmetric Pipelined Burst SRAM (R) Recommended Operating Conditions Symbol Parameter VDD VDDQ Vih Vil Voh Vol Toprc Topri Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Commercial Operating Temp. Industrial Operating Temp. Condition 2.5V 5% 2.5V 5% Min 2.375 2.375 1.7 -0.3 Max 2.625 2.625 VDDQ + .8 0.7 Units V V V V V Ioh = -1 mA Iol = 1 mA 2.0 0.2 0 -40 70 85 V C C Units V V ns ns Absolute Maximum AC Operating Conditions Symbol Parameter Vih Vil tOVR tSET Input High Voltage Input Low Voltage Overshoot/Undershoot Voltage Duration Overshoot/Undershoot Settling Time Min 1.7 VSSQ - 1.0 Max VDDQ+1.0 0.7 0.2*tCY 0.8*tCY Maximum DC Current Requirements Symbol IDD IDD1 IDDZ Condition Current 150 40 20 Units mA mA mA Operating current, device selected; all inputs < Vil or > Vih; cycle time > 7.5ns, VDD= max, 0 pF load Idle current; ADV/LD#, GW#, BW#s, CKE# and all other inputs > 2.8 volts; cycle time > tKC min, VDD= max, 0 pF load Sleep mode, clock stopped, all inputs > 2.8 v, VDD= max www..com DS15, Rev 0.5 - 10/14/00 Preliminary Information Page 5 (c) 2000 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 www..com MC805256K36 MOSYS 9-Mbit: 256Kx36 Symmetric Pipelined Burst SRAM (R) AC Timing Characteristics at Recommended Operating Conditions -5 (200 MHz) Sym tKEH tKES tAAH tAAS tAH tAS tCEH tCES tDH tDS tWS tWH tKC tKH tKL tKQ tKQHZ tKQLZ tKQX tOELZ tOEHZ tOEQ tOEQX tZZ tZZR tZZHZ tZZLZ Parameter CKE# hold CKE# setup ADV/LD# hold ADV/LD# setup Address hold Address setup Chip Enable hold Chip Enable setup Write Data hold Write Data setup WE#, BWx# setup WE#, BWx# hold Clock cycle Clock high Clock low Clock to output valid Clock to output high-Z Clock to output low-Z Clock to output invalid OE# to output low-Z OE# to output high-Z OE# to output valid OE# to output invalid ZZ activation ZZ deactivation ZZ to DQ Hi-Z ZZ to DQ Lo-Z 0 0 2 5 100 0 1.5 1.5 1.5 0 3 3 0 2 5 100 0 Min 0.5 1.3 0.5 1.3 0.5 1.3 0.5 1.3 0.5 1.3 1.3 0.5 5 2 2 3 2.9 1.5 1.5 1.5 0 3.5 3.5 0 2 5 100 Max -6 (166 MHz) Min 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 1.5 0.5 6 2.5 2.5 3.5 3.1 1.5 1.5 1.5 0 4.2 4.2 Max -7R5 (133 MHz) Min 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 1.7 0.5 7.5 3 3 4.2 3.8 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tKC tKC tKC tKC www..com DS15, Rev 0.5 - 10/14/00 Preliminary Information Page 6 (c) 2000 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 www..com MC805256K36 MOSYS 9-Mbit: 256Kx36 Symmetric Pipelined Burst SRAM (R) tKC CLK txH CKE# txS tKH tKL CE1# ADV/LD# WE# BWx# Address A1 A2 A3 A4 tKQ A5 A6 tKQHZ A7 DQ wDA1 wDA2 wDA2+1 tKQLZ rA3 rA4 rA4+1 tOEQ tOELZ wDA5 rA6 tOEHZ OE# Read/Write Timing CLK CKE# CE1# ADV/LD# WE# BWx# Address A1 A2 A3 A4 A5 DQ wDA1 rA2 rA3 wDA4 rA5 www..com NOP, Stall, Deselect Timing DS15, Rev 0.5 - 10/14/00 Preliminary Information Page 7 (c) 2000 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 www..com MC805256K36 MOSYS 9-Mbit: 256Kx36 Symmetric Pipelined Burst SRAM (R) tKC CLK tKH ADV/LD# tKL ZZ tZZ Adr/CMD Deselect/Rd tZZHZ DQ Deselect/Rd tZZLZ tZZR Any cmd Any cmd ZZ Timing Test and Measurement Test Structure and Measurement Points Notes 1 2 Valid Delay Measurement is made from the VDDQ / 2 on the input waveform to the VDDQ / 2 on the output waveform. Input waveform should have a slew rate of 1V/ns. Tri-state toff measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20% from its initial to final value VDDQ/2. Tri-State Measurement Input Waveform Output Waveform VH VL t OFF VDDQ 2 t ON VH -(0.2(V -VZ )) V +(0.2(V -V )) H Z H L VZ VZ -(0.2(VH-VL )) 0.2(VZ -VL ) Z 0 = 50 W Output Buffer Output Waveform Input Waveform TDLY Measurement VDDQ 2 t PLH VDDQ 2 tPHL Output Load 50 W VL = 30 pf Capacitive load consists VSS of all components of the test environment. VDDQ 2 www..com DS15, Rev 0.5 - 10/14/00 Preliminary Information Page 8 (c) 2000 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 www..com MC805256K36 MOSYS 9-Mbit: 256Kx36 Symmetric Pipelined Burst SRAM (R) Figure 1. LQFP Mechanical Characteristics www..com DS15, Rev 0.5 - 10/14/00 Preliminary Information Page 9 (c) 2000 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94085 |
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